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L6562
TRANSITION-MODE PFC CONTROLLER
s s s s s s s s s s s
TRANSITION-MODE CONTROL OF PFC PREREGULATORS PROPRIETARY MULTIPLIER DESIGN FOR MINIMUM THD OF AC INPUT CURRENT VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION ULTRA-LOW (70A) START-UP CURRENT LOW (4 mA) QUIESCENT CURRENT EXTENDED IC SUPPLY VOLTAGE RANGE ON-CHIP FILTER ON CURRENT SENSE DISABLE FUNCTION 1% (@ Tj = 25 C) INTERNAL REFERENCE VOLTAGE -600/+800mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN AND VOLTAGE CLAMP MINIDIP/SO8 PACKAGES
BCD TECHNOLOGY
Minidip (DIP-8)
SO8
ORDERING NUMBERS: L6562N L6562D
DESCRIPTION The L6562 is a current-mode PFC controller operating in Transition Mode (TM). Pin-to-pin compatible with the predecessor L6561, it offers improved performance. The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows wide-range-mains operation with an extremely low THD, even over a large load range.
APPLICATIONS PFC PRE-REGULATORS FOR:
s s s
IEC61000-3-2 COMPLIANT SMPS (TV, DESKTOP PC, MONITOR) UP TO 300W HI-END AC-DC ADAPTER/CHARGER ENTRY LEVEL SERVER & WEB SERVER
BLOCK DIAGRAM
COMP 2 1 INV + 2.5V 5pF VCC MULTIPLIER AND THD OPTIMIZER 40K MULT 3 4 CS
VOLTAGE REGULATOR
OVERVOLTAGE DETECTION
+
-
8 VCC 25 V R1 + R2 VREF2 ZERO CURRENT DETECTOR + 2.1 V 1.6 V STARTER
-
INTERNAL SUPPLY 7V R S DRIVER Starter stop Q 15 V 7 GD UVLO
DISABLE 6 GND 5 ZCD
May 2003
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L6562
The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj = 25C) internal voltage reference. The device features extremely low consumption (70 A before start-up and <4 mA running) and includes a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS's up to 300W. ABSOLUTE MAXIMUM RATINGS
Symbol VCC IGD --IZCD Ptot Tj Tstg Pin 8 7 1 to 4 5 Parameter IC Supply voltage (Icc = 20 mA) Output Totem Pole Peak Current Analog Inputs & Outputs Zero Current Detector Max. Current Power Dissipation @Tamb = 50C Junction Temperature Operating range Storage Temperature (Minidip) (SO8) Value self-limited 0.8 -0.3 to 8 -50 (source) 10 (sink) 1 0.65 -40 to 150 -55 to 150 Unit V A V mA W C C
PIN CONNECTION (Top view)
INV COMP MULT CS
1 2 3 4
8 7 6 5
Vcc GD GND ZCD
THERMAL DATA
Symbol Rth j-amb Parameter Max. Thermal Resistance, Junction-to-ambient SO8 150 Minidip 100 Unit C/W
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L6562
PIN DESCRIPTION
N 1 2 3 4 Pin INV COMP MULT CS Function Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. Output of the error amplifier. A compensation network is placed between this pin and INV (pin #1) to achieve stability of the voltage control loop and ensure high power factor and low THD. Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine MOSFET's turn-off. Boost inductor's demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET's turn-on. Ground. Current return for both the signal part of the IC and the gate driver. Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper limit is extended to 22V min. to provide more headroom for supply voltage changes.
5 6 7
ZCD GND GD
8
Vcc
ELECTRICAL CHARACTERISTICS (Tj = -25 to 125C, VCC = 12, CO = 1 nF; unless otherwise specified)
Symbol SUPPLY VOLTAGE VCC VCCon VCCOff Hys VZ Istart-up Iq ICC Iq Operating range Turn-on threshold Turn-off threshold Hysteresis Zener Voltage Start-up Current Quiescent Current Operating Supply Current Quiescent Current ICC = 20 mA Before turn-on, VCC =11V After turn-on @ 70 kHz During OVP (either static or dynamic) or VZCD =150 mV VVFF = 0 to 4 V 0 to 3 VMULT = 0 to 0.5V VCOMP = Upper clamp VMULT = 1 V, VCOMP = 4 V 1.65 1.9 After turn-on
(1) (1)
Parameter
Test Condition
Min. 10.3 11 8.7 2.2 22
Typ.
Max. 22
Unit V V V V V A mA mA mA
12 9.5 25 40 2.5 3.5
13 10.3 2.8 28 70 3.75 5 2.2
SUPPLY CURRENT
MULTIPLIER INPUT IMULT VMULT V CS --------------------VMULT K Input Bias Current Linear Operation Range Output Max. Slope -1 A V V/V
Gain (2)
0.5
0.6
0.7
1/V
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L6562
ELECTRICAL CHARACTERISTICS (continued) (Tj = -25 to 125C, VCC = 12, CO = 1 nF; unless otherwise specified)
Symbol ERROR AMPLIFIER VINV Voltage Feedback Input Threshold Line Regulation IINV Gv GB ICOMP VCOMP Input Bias Current Voltage Gain Gain-Bandwidth Product Source Current Sink Current Upper Clamp Voltage Lower Clamp Voltage CURRENT SENSE COMPARATOR ICS td(H-L) VCSoffset Input Bias Current Delay to Output VCOMP = Upper clamp VMULT = 0 VMULT = 2.5V ZERO CURRENT DETECTOR VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk VZCDdis VZCDen IZCDres STARTER tSTART IOVP Hys Start Timer period Dynamic OVP triggering current Hysteresis Static OVP threshold GATE DRIVER VOH Dropout Voltage VOL IGDsource = 20 mA IGDsource = 200 mA IGDsink = 200 mA 2 2.5 0.9 2.6 3 1.9 V V
(3) (1)
Parameter
Test Condition Tj = 25 C 10.3 V < Vcc < 22 V Vcc = 10.3 V to 22V VINV = 0 to 3 V Open loop VCOMP = 4V, VINV = 2.4 V VCOMP = 4V, VINV = 2.6 V ISOURCE = 0.5 mA ISINK = 0.5 mA VCS = 0
(1)
(1)
Min. 2.465 2.44
Typ. 2.5
Max. 2.535 2.56
Unit V
2 60 -2 2.5 5.3 2.1 80 1 -3.5 4.5 5.7 2.25
5 -1
mV A dB MHz
-5 6 2.4
mA mA V V
-1 200 1.6 1.7 30 5 5.0 0.3 5.7 0.65 2.1 1.6 2 -2.5 2.5 150 30 200 75 250 350 -5.5 6.5 1 350 1.8
A ns V mV
VCS clamp Current sense reference clamp Current sense offset
Upper Clamp Voltage Lower Clamp Voltage Arming Voltage (positive-going edge) Triggering Voltage (negative-going edge) Input Bias Current Source Current Capability Sink Current Capability Disable threshold Restart threshold Restart Current after Disable
IZCD = 2.5 mA IZCD = -2.5 mA
(3) (3)
V V V V A mA mA mV mV A
VZCD = 1 to 4.5 V
75
130
300
s
OUTPUT OVERVOLTAGE 35 2.1 40 30 2.25 2.4 45 A A V
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L6562
ELECTRICAL CHARACTERISTICS (continued) (Tj = -25 to 125C, VCC = 12, CO = 1 nF; unless otherwise specified)
Symbol tf tr VOclamp Parameter Voltage Fall Time Voltage Rise Time Output clamp voltage UVLO saturation
(1) (2) (3)
Test Condition
Min.
Typ. 30 40
Max. 70 80 15 1.1
Unit ns ns V V
IGDsource = 5mA; Vcc = 20V VCC = 0 to VCCon, Isink=10mA
10
12
All parameters are in tracking The multiplier output is given by: V cs = K V M ULT ( V C OMP - 2.5 ) Parameters guaranteed by design, functionality tested in production.
TYPICAL ELECTRICAL CHARACTERISTICS Figure 1. Supply current vs. Supply voltage
ICC (mA) 10 5 1 0.5 0.1 0.05 0.01 0.005 0 0 5 10 15 Vcc(V) 20 25 Co = 1nF f = 70 kHz Tj = 25C
2 1 0.5 0.2 0.1 0.05 0.02 -50 Before start-up Vcc = 12 V Co = 1 nF f = 70 kHz Disabled or during OVP
Figure 3. IC consumption vs. Tj
Icc 10 [mA] 5
Operating Quiescent
0
50
100
150
Tj (C)
Figure 2. Start-up & UVLO vs. Tj
12.5 VCC-ON (V) 12 11.5
Figure 4. Vcc Zener voltage vs. Tj
VccZ 28 (V)
27 26
11
25
10.5 10 VCC-OFF 9.5 (V) 9 -50 0 50 Tj (C) 100 150
24 23 22 -50
0
50
100
150
Tj (C)
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L6562
Figure 5. Feedback reference vs. Tj
VREF 2.6 (V)
Vcc = 12 V
Figure 8. Delay-to-output vs. Tj
tD(H-L) (ns)
Vcc = 12 V
500
2.55
400
300
2.5
200
2.45
100
2.4 -50
0
50
Tj (C)
100
150
0 -50
0
50 Tj (C)
100
150
Figure 6. OVP current vs. Tj
IOVP (A)
Figure 9. Multiplier characteristic
VCS (pin 4) (V) upper voltage
Vcc = 12 V
clamp
41
VCOMP(pin 2) (V)
3.5 5.0
1.6
4 .5
40.5
1.4 1.2
4.0 3.2
40
1.0 0.8 0.6
3.0
39.5
0.4 0.2
39 -50 0 50
Tj (C)
2.8 2.6
100
150
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VMULT(pin 3) (V)
Figure 7. E/A output clamp levels vs. Tj
Vpin2 (V) 6 Upper clamp 5
Vcc = 12 V
Figure 10. Multiplier gain vs. Tj
K 1
Vcc = 12 V VCOMP =4 V VMULT =1V
0.8
0.6
4
0.4
3 Lower clamp 2 -50
0.2
0
50 Tj (C)
100
150
0 -50
0
50 Tj (C)
100
150
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L6562
Figure 11. Vcs clamp vs. Tj
VCSx 2 (V)
Figure 14. ZCD source capability vs. Tj
IZCDsrc 0 (mA)
Vcc = 12 V VZCD= lower clamp
1.8
-2
1.6
-4
1.4 1.2 1 -50
Vcc = 12 V VCOMP= Upper clamp
-6
0
50
Tj (C)
100
150
-8 -50
0
50 Tj (C)
100
150
Figure 12. Start-up timer vs. Tj
Tstart 150 (s)
140
Figure 15. Gate-drive output low saturation
Vpin7 [V]
Vcc = 12 V
4
Tj = 25 C Vcc = 11 V SINK
3
130
2
120
110
1
100 -50
0
0 50 100 150
0
200
400
600
800
1,000
Tj (C)
IGD[mA]
Figure 13. ZCD clamp levels vs. Tj
V ZCD (V)
Figure 16. Gate-drive output high saturation
Vpin7[V]
-1.5
7 6 5 4
Upper clamp
-2 Vcc - 2.0
Vcc = 12 V I ZCD = 2.5 mA
Tj = 25 C Vcc = 11 V SOURCE
Vcc - -2.5 2.5
-3 Vcc - 3.0
3
Vcc - -3.5 3.5
2 1 0 -50 0 50
Tj (C)
-4 Vcc - 4.0
Lower clamp
-4.5
100
150
0
100
200
300
400
500
600
700
IGD[mA]
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L6562
Figure 17. Gate-drive clamp vs. Tj
Vpin7clamp 15 (V)
Vcc = 20 V
Figure 18. UVLO saturation vs. Tj
Vpin7 (V) 1.1
Vcc = 0 V
14
1 0.9
13
0.8
12
0.7
11
0.6 0.5 -50
10 -50
0
50 Tj (C)
100
150
0
50 Tj (C)
100
150
APPLICATION INFORMATION Overvoltage protection Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple components, the current through R1, IR1, equals that through R2, IR2. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then: 2.5 Vo - 2.5 I R2 = ------- = I R1 = --------------------- . R2 R1 If the output voltage experiences an abrupt change Vo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why Vo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become: I' R1 = Vo - 2.5 + Vo . --------------------------------------R1 The difference current IR1=I'R1-IR2=I'R1-IR1=Vo/R1 will flow through the compensation network and enter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about 37 A the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the output. As the current exceeds 40 A, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is maintained until the current falls below approximately 10 A, which re-enables the internal starter and allows switching to restart. The output Vo that is able to trigger the Dynamic OVP function is then: Vo = R1 40 10
-6
.
An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on Vo. Since Vo << Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo = 400 V, Vo = 40 V. Then: R1=40V/40A=1M; R2=1M*2.5/(400-2.5)=6.289k. The tolerance on the OVP level due to the L6562 will be 40*0.12=4.8V, that is 1.2% of the regulated value. When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier out-
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L6562
put will saturate low; hence, when this is detected, the external power transistor is switched off and the IC put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its linear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low. When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply system. THD optimizer circuit The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. Figure 19. THD optimization: standard TM PFC controller (left side) and L6562 (right side)
Input current
Input current
Rectified mains voltage
Rectified mains voltage
Imains Input current Vdrain MOSFET's drain voltage
Imains Input current Vdrain MOSFET's drain voltage
To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the highfrequency filter capacitor after the bridge. The effect of the circuit is shown in figure 19, where the key waveforms of a standard TM PFC controller are compared to those of the L6562. Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the
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L6562
instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC preregulator - thus making the action of the optimizer circuit little effective. Figure 20. Typical application circuit (250W, Wide-range mains)
D3 1N5406
R4 R5 180 k 180 k T D8 1N4150 C5 12 nF R14 100 R6 68 k R50 10 k C3 2.2 F R12 750 k D1 STTH5L06 NTC 2.5 R11 750 k Vo=400V Po=250W
R1 1.5 M
D2 1N5248B
BRIDGE FUSE 5A/250V + STBR606
C1 1 F 400V
C23 680 nF R2 1.5 M 8 3 5 2 1 7 4 R7 10 C6 100 F 450V
Vac (85V to 265V)
-
L6562
6
MOS STP12NM50
7 C/W heat sink
C2 10nF R3 22 k
C29 22 F 25V
C4 100 nF
R9 0.33 1W
R10 0.33 1W
R13 9.53 k
-
Boost Inductor Spec ETD29x16x10 core, 3C85 ferrite or equivalent 1.5 mm gap for 150 H primary inductance Primary: 74 turns 20xAWG30 ( 0.3 mm) Secondary: 8 turns 0.1 mm
Figure 21. Demo board (EVAL6562N, 80W, Wide-range mains): Electrical schematic
R4 R5 180 k 180 k
T D8 1N4150 C5 12 nF R14 100 R6 68 k R50 12 k C3 680 nF R12 750 k D1 STTH1L06 NTC 2.5 R11 750 k Vo=400V Po=80W
R1 750 k
D2 1N5248B
BRIDGE FUSE 4A/250V + DF06M
C1 0.47 F 400V
C23 330 nF R2 750 k 8 3 5 2 1 7 4 R7 33 C6 47 F 450V
Vac (85V to 265V)
-
L6562
6
MOS STP8NM50
C2 10nF R3 10 k
C29 22 F 25V
C4 100 nF
R9 0.82 0.6 W
R10 0.82 0.6 W
R13 9.53 k
-
Boost Inductor Spec (ITACOIL E2543/E) E25x13x7 core, 3C85 ferrite 1.5 mm gap for 0.7 mH primary inductance Primary: 105 turns 20x0.1 mm Secondary: 11 turns 0.1 mm
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L6562
Figure 22. EVAL6562N: PCB and component layout (Top view, real size: 57 x 108 mm)
Table 1. EVAL6562N: Evaluation results at full load
Vin (VAC) Pin (W) Vo (VDC) Vo(Vpk-pk) Po (W) (%) PF THD (%)
85 110 135 175 220 265
86.4 84.6 83.8 83.2 82.9 82.7
394.79 394.86 394.86 394.87 394.87 394.87
12.8 12.8 12.8 15.5 15.7 15.9
80.16 80.20 80.20 80.20 80.20 80.20
92.8 94.8 95.7 96.4 96.7 97.0
0.998 0.996 0.991 0.981 0.956 0.915
3.6 4.2 4.9 6.5 7.8 9.2
Note: measurements done with the line filter shown in figure 23
Table 2. EVAL6562N: Evaluation results at half load
Vin (VAC) Pin (W) Vo (VDC) Vo(Vpk-pk) Po (W) (%) PF THD (%)
85 110 135 175 220 265
42.8 42.5 42.5 42.5 42.6 42.6
394.86 394.90 394.91 394.93 394.94 394.94
6.6 6.6 6.7 8.0 8.2 8.3
40.20 40.20 40.20 40.19 40.19 40.19
93.9 94.6 94.6 94.6 94.3 94.3
0.994 0.985 0.967 0.939 0.869 0.776
5.5 6.2 7.1 8.3 9.8 11.4
Note: measurements done with the line filter shown in figure 23
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L6562
Table 3. EVAL6562N: No-load measurements
Vin (VAC) Pin (W) Vo (VDC) Vo(Vpk-pk) Po (W)
85 110 135 175 (*) 220 (*) 265 (*)
(*)
0.4 0.3 0.3 0.4 0.4 0.5
396.77 396.82 396.83 396.90 396.95 396.98
0.45 0.55 0.60 1.00 1.40 1.65
0 0 0 0 0 0
Vcc = 12V supplied externally
Figure 23. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation
to the AC source
B81133 470 nF, X2 EPCOS B82732 47 mH, 1.3A EPCOS
B81133 680 nF, X2 EPCOS
to EVAL6562N
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L6562
mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch
OUTLINE AND MECHANICAL DATA
Minidip
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L6562
DIM. MIN. A a1 a2 a3 b b1 C c1 D (1) E e e3 F (1) L M S 3.8 0.4 4.8 5.8 0.65 0.35 0.19 0.25 0.1
mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 0.026 0.014 0.007 0.010 0.004 MIN.
inch TYP. MAX. 0.069 0.010 0.065 0.033 0.019 0.010 0.020
OUTLINE AND MECHANICAL DATA
45 (typ.) 5.0 6.2 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.15 0.016 0.189 0.228 0.050 0.150 0.157 0.050 0.024 0.197 0.244
SO8
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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L6562
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. STMicroelectronics acknowledges the trademarks of all companies referred to in this document. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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